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The second hardware more » trend is the growing gap between memory bandwidth and the aggregate speed-that is, the sum of all cores' computing power-of a Chip Multiprocessor (CMP). Some evidences are already shown on Graphic Processing Units (GPU): Irregular data accesses (e.g., indirect references A]) and conditional branches are limiting many GPU applications' performance at a level an order of magnitude lower than the peak of GPU. With more processors produced through a massive integration of simple cores, future systems will increasingly favor regular data-level parallel computations, but deviate from the needs of applications with complex patterns. The first is the increasing sensitivity of processors' throughput to irregularities in computation. The development of modern processors exhibits two trends that complicate the optimizations of modern software. Using a suite of important computational kernels and complete scientific applications, they examine performance differences resulting both from the CC-NUMA/ICOMA nature of the machines as well as from specific differences in system implementation. In this paper, the authors compare the parallel performance of a recent realization of each more » type of architecture-the Stanford DASH multiprocessor (CC-NUMA) and the Kendall Square Research KSR-1 (COMA). Previous work had discussed the general advantages and disadvantages of the two types of architectures, and presented results comparing the performance of small problems on simulated architectures of the two types. While both architectures migrate and replicate data at the cache level automatically under hardware control, COMA machines do this at the main memory level as well. Both have distributed main memory and use directory-based cache coherence. Two interesting variants of large-scale shared-address-space parallel architectures are cache-coherent non-uniform-memory-access machines (CC-NUMA) and cache-only memory architectures (COMA).

As part of this research ISI developed a compiler that recognizes transactional memory “pragmas” and automatically generates parallel code for the TM programming model = , In addition to the selective coherence studies on the FLASH machine, in the last six months of this project ISI performed research on compiler technology for the transactional memory (TM) programming model being developed at Stanford. We also present data on the SpecOMP benchmarks, showing that the protocols have a modest overhead of less than 3% in applications where the alternative mechanisms are not needed. In LS-DYNA, we obtain improvements of 18% on average using the non-coherent version. For RandomAccess, the non-coherent and write-update versions can outperform the coherent version by factors of 5 and 2.5, respectively. We present data on two computations, RandomAccess from the HPC Challenge benchmarks and a forward solver derived from LS-DYNA, showing the performance advantages of the alternative coherence mechanisms.

Such an approach has the advantages of using alternative coherence only more » where it is beneficial, and also provides an evolutionary migration path for improving application performance. This report describes an actual implementation of a set of coherence protocols that support coherent, non-coherent and write-update accesses for a CC-NUMA shared-memory architecture, the Stanford FLASH machine.

Alternative coherence mechanisms have often been discussed as a means for reducing unintended communication, although architecture implementations of such mechanisms are quite rare. In this project, we developed and evaluated a collection of hardware, compiler, languages and performance monitoring tools to obtain high performance on scientific and engineering applications on NUMA platforms by managing communication through alternative coherence mechanisms. Because communication between processors is managed implicitly by the hardware, rather than expressed by the programmer, application performance may suffer from unintended communication – communication that the programmer did not consider when developing his/her application. In spite of the programming advantages of shared-memory platforms, obtaining good performance for large scientific and engineering applications on such machines can be challenging.

ABSTRACT The goal of this project was to improve the performance of large scientific and engineering applications through collaborative hardware and software mechanisms to manage the memory hierarchy of non-uniform memory access time (NUMA) shared-memory machines, as well as their component individual processors.

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